Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are connected by means of electrically conductive features to form complex circuits, such as memory devices, logic devices, and microprocessors. Multiple conductive layers are formed over individual circuit elements in and on a semiconductor substrate and are typically separated from each other by insulating dielectric layers. The conductive layers are often selectively connected or “wired” together in order to allow for conduction of electricity in a desired pattern. One means of connecting conductive layers is through the formation of a via at an interconnection between conductive layers. Vias are channels or plugs of conductive material. Interconnections between multiple conductive layers may be formed by a series of vias, i.e., a via chain.
During the formation of a via, problems may arise from high contact resistance between the via material and the region of the conductive layer to which it contacts, or through void or seam formation within the via. However, integrated circuit performance requires that the vias have substantially uniform resistances.
Therefore, it is desirable to measure the resistances of vias to ensure proper integrated circuit performance. However, along with the miniaturization of device features of modern, ultra-high density integrated circuits, vias have decreased in size such that measurement of via resistance is difficult. Specifically, typical testing tools struggle to measure accurately in the microvolt (μV) differential voltage range. Further, noise and offset levels are substantial in the μV range. At the same time, current cannot be raised to overcome the testing limitations as the vias under testing generally cannot carry high currents. Specifically, high current densities lead to overheating and destruction of the vias. As a result, it is difficult to measure the resistance of vias that have low resistance and low current carrying capacity.
Accordingly, it is desirable to provide improved structures and methods for testing integrated circuits and via chains therein. Further, it is desirable to provide structures and methods for measuring resistances of via chains in integrated circuits. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.